1. Field of the Invention
The present invention generally relates to semiconductor memory devices and, more particularly, to dynamic semiconductor memory devices having memory cells that require refresh.
2. Description of the Related Art
The evolution of sub-micron CMOS technology has resulted in an increasing demand for high-speed semiconductor memory devices, such as dynamic random access memory (DRAM) devices, pseudo static random access memory (PSRAM) devices, and the like. Herein, such memory devices are collectively referred to as DRAM devices. Such devices utilize memory cells consisting of one transistor and one capacitor. Due to leakage, the memory cells require periodic refreshing to protect data that is stored in the memory cell from corruption or decaying over time. The data stored in the memory cell is automatically restored to a full logic level when accessed (e.g., via a read or write operation), but must be periodically refreshed when not accessed. Therefore, DRAM devices typically include refresh circuitry to facilitate memory cell refresh.
FIG. 1 illustrates an exemplary DRAM device 100 utilizing a conventional refresh circuit 120 to refresh rows of memory cells arranged in four banks (1040-1043). As illustrated, the refresh circuit 120 generally includes a refresh timer 122 and a refresh address counter 126. The refresh timer 122 is enabled when a self-refresh mode is entered, in response to a command decoder 112 detecting a self-refresh command issued by an external device via a command bus 128. When enabled, the refresh timer generates periodic refresh request (REFRESH_REQUEST) signals that initiate refresh operations via bank control logic 106. The frequency of the refresh request signals is selected to ensure each row is accessed within a minimum specified retention time of the memory cells.
In response to a refresh request signal, the bank control logic refreshes a row of memory indicated by the row address (RA) generated by the refresh address counter 126. The upper bits of the row address may indicate which bank 104 contains the row to be refreshed. The refresh request signal may also enable a delay circuit 124, the output of which signals the refresh address counter to increment the row address. As illustrated, via an OR gate 128, external refresh commands (e.g., auto-refresh commands), may also initiate a refresh request and signal the refresh address counter to increment the row address.
Because each row of cells must be accessed within a specified cell retention time, refresh operations occur frequently. As a result, refreshing memory cells is a power-consuming routine. In battery-powered computer systems (e.g., palm-top computers, mobile and hand-held electronic devices, and the like), minimization of power consumption is critically important. One method that may reduce the power consumption of the memory is known in the art as a partial array refresh (PAR) scheme. Using the PAR scheme in DRAM devices having a plurality of memory banks, only the memory banks where the memory cells contain valid data are refreshed.
FIG. 2 depicts a logical diagram of an exemplary PAR scheme for use in a DRAM device having four banks (1040-1043). Bits in a mode register (e.g., a mode register 114, as shown in FIG. 1) may be programmed (e.g., via a mode register set command) to determine over what address range refresh operations will take place. As illustrated, all four banks, the first two banks, the first bank, or only half of the first bank may be selected. The self-refresh current will be proportional to the number of banks selected. For example, self-refresh current may be reduced by 50% if only the first two banks are selected.
However, one disadvantage with PAR schemes, is that the performance of multiple bank memories, such as DRAMs and double data rate (DDR) DRAMs, is often optimized by interleaving operations involving different banks, such that certain latencies associated with accessing each bank are hidden. As an example, by operating two or more banks in an interleaved manner, precharge time, or the time from a bank active to column access, may be hidden. If only one bank is chosen in a PAR scheme, however, multiple bank operation is no longer an available option. Another disadvantage with PAR schemes is that it is not likely all memory cells in a selected bank actually contain valid data. As a result, the power savings is not maximized, as a number rows that do not contain valid data continue to be refreshed.
Accordingly, there is a need in the art for an improved method and circuit configuration for refreshing data in semiconductor memory devices.